Re: [fpu] supported FP operations

[Jamil Khatib <jamilkhatib75@yahoo.com>]

OK I'll do them also but because it is simple to use
the fmul to implement teh fdiv it will be much easier
for a begginer in verilog, I just start studying
veriolg and looking for floating point dividers.

But I do not have the latest fmul code to start with.


--- Damjan Lampret <damjanlampret@yahoo.com> wrote:
> Jamil,
> 
> I think it would be better if you develop SQRT and
> conversions
> (integer->SF and SF->integer). Divide is simple
> enough to utilize fmul
> and just replace appropriate blocks. Right?

May be there are more exceptions and cases

> 
> At this point I don't care if every FP operation has
> unique pipeline. A
> lot of silicon but we don't have die constraints. So
> waste silicon...
if we do not use enough pipelines we will have some
problems with speed, do not we?


> ;-)
> 
> --damjan


Jamil Khatib



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