RE: [usb] USB 2.0 core Spec. First Draft

["Peter Teng" <peter_teng@el.nec.com>]

Rudolf,

	Thanks for the great job that you have put forward.
	I have a few comments below:
	1. Why is a link list architecture is picked for endpoint definition? This
endpoint definition has to be ran in real time negotiating the external PHY
for appropriate responses to the incoming traffic. This imposes the finite
latency from the time a USB transaction is received and the time a proper
response shall be generated based upon the endpoint targeted. With the link
list, the search time varies with endpoint information location within the
linked list. And further more each search involves read, compare and fetch
next. This gives undeterministric behavior for endpoint responses.
	2. There are quite a number of empty bit space for link list entry. They
should be able to fit all in two 32 bit space instead. And in addition, it
is better to have +2 counter instead of +3 counter for search engine to
forward to the next entry (in case linked list architecture is used)
	3. What are the conditions for the hardware to assert the HALT interrupt?
	4. What are the number of transactions per uframe register for?
	5. What does the share bit in 3.1.2 for?
	6. How does the TBD of TBD register in 3.1.2 for interrupt acknowledge
associated the linked list entry? How does the software above the layer
understand interrupt is generated by which endpoint?
	7. No register read clearing is preferred. This forces the software to have
variable storing the register's content after reading it. This in effect
forces the software to have layer hierarchy of having lower layer to take
care of all the register read/write protocol, instead of having different
driver stacks of equal right to access the registers.
	8. What is default endpoint?
	9. Interrupt source register only contains the endpoint information which
requires the software in reading the content in time before next transaction
occurs. This imposes a very big challenge for the software developer to put
a finite constraint of the software behavior. I would prefer to see a
register have 32 bit corresponding to each out endpoints and another
register have 32 bit corresponding to each in endpoints. For assertion of
each bit, it means the interrupt for each endpoint accordingly.
	10. Why there are two different interrupt pins? Are they prioritized? If
so, which interrupt is associated with higher, which is for lower?
	11. Does the spec impose any buffer alignment requirement? For example, a
512 byte buffer shall be located in the 512 byte aligned buffer space? If
so, fewer counter bits can be used to save gatecount.

best regards,
Peter

-----Original Message-----
From: owner-usb@opencores.org [mailto:owner-usb@opencores.org]On Behalf
Of Rudolf Usselmann
Sent: Monday, January 08, 2001 4:10 AM
To: USB Mailing List
Cc: Damjan Lampret
Subject: [usb] USB 2.0 core Spec. First Draft



Attached is the first draft of the USB 2.0 IP core specification.

It is far from being complete, however I thought I post it to get
some feedback on the architectural organization.

Anu comments and suggestions welcomed !

Thanks,
rudi