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[fpu] fmul synthesis
I also synthesized fmul (version in the CVS). Clock cycle of 8.95ns.
Same libs and operating conditions (2.5v, 25c). If operating conditions
are changed to 2.75v and temp 0c then you get about 10% better
performance. Power requirements (according to DC) are roughly about
283mW (I forgot to mention power requirments for fasu which are about
123mW). Numbers for power are probably very rough since DC doesn't have
a clue what typical input vectors are.
--damjan
****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : fmul
Version: 1999.10
Date : Mon Jul 17 16:17:18 2000
****************************************
Operating Conditions: typical Library: typical
Wire Load Model Mode: segmented
Startpoint: opa_r_reg_1_
(rising edge-triggered flip-flop clocked by clk)
Endpoint: u3/prod_reg_44_
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
mul24_r TSMC25_Conservative typical
fmul TSMC25_Conservative typical
norm_mul TSMC25_Conservative typical
mul24_r_DW02_mult_24_24_0
TSMC25_Conservative typical
mul24_r_DW01_add_46_0
TSMC25_Conservative typical
Point Incr
Path
--------------------------------------------------------------------------
clock clk (rise edge) 0.00
0.00
clock network delay (ideal) 0.00
0.00
opa_r_reg_1_/CK (DFFX4) 0.00
0.00 r
opa_r_reg_1_/Q (DFFX4) 0.25
0.25 f
u3/opa_1_ (mul24_r) 0.00
0.25 f
u3/mul_37/A_1_ (mul24_r_DW02_mult_24_24_0) 0.00
0.25 f
u3/mul_37/U78/Y (BUFX12) 0.20
0.45 f
u3/mul_37/U655/Y (NAND2X4) 0.15
0.60 r
u3/mul_37/U638/Y (XOR2X4) 0.23
0.83 r
u3/mul_37/S2_2_13/S (ADDFHX4) 0.25
1.08 f
u3/mul_37/S2_3_12/CO (ADDFHX4) 0.23
1.30 f
u3/mul_37/S2_4_12/CO (ADDFHX4) 0.30
1.60 f
u3/mul_37/S2_5_12/CO (ADDFHX4) 0.30
1.90 f
u3/mul_37/S2_6_12/CO (ADDFHX4) 0.30
2.21 f
u3/mul_37/S2_7_12/CO (ADDFHX4) 0.30
2.51 f
u3/mul_37/S2_8_12/CO (ADDFHX4) 0.30
2.81 f
u3/mul_37/S2_9_12/CO (ADDFHX4) 0.30
3.11 f
u3/mul_37/S2_10_12/CO (ADDFHX4) 0.30
3.41 f
u3/mul_37/S2_11_12/CO (ADDFHX4) 0.30
3.71 f
u3/mul_37/S2_12_12/CO (ADDFHX4) 0.30
4.01 f
u3/mul_37/S2_13_12/CO (ADDFHX4) 0.30
4.31 f
u3/mul_37/S2_14_12/CO (ADDFHX4) 0.30
4.61 f
u3/mul_37/S2_15_12/CO (ADDFHX4) 0.30
4.91 f
u3/mul_37/S2_16_12/CO (ADDFHX4) 0.30
5.21 f
u3/mul_37/S2_17_12/CO (ADDFHX4) 0.30
5.51 f
u3/mul_37/S2_18_12/S (ADDFHX4) 0.32
5.84 f
u3/mul_37/S2_19_11/CO (ADDFHX4) 0.30
6.14 f
u3/mul_37/S2_20_11/CO (ADDFHX4) 0.30
6.44 f
u3/mul_37/S2_21_11/S (ADDFHX4) 0.32
6.76 f
u3/mul_37/S2_22_10/CO (ADDFHX4) 0.30
7.06 f
u3/mul_37/S4_10/CO (ADDFHX4) 0.30
7.37 f
u3/mul_37/S14_34/CO (ADDFHX4) 0.35
7.72 f
u3/mul_37/FS/B_33_ (mul24_r_DW01_add_46_0) 0.00
7.72 f
u3/mul_37/FS/U133/Y (NOR2X4) 0.17
7.89 r
u3/mul_37/FS/U131/Y (NOR3X2) 0.11
8.00 f
u3/mul_37/FS/U83/Y (OAI2BB1X4) 0.14
8.15 r
u3/mul_37/FS/U123/Y (INVX8) 0.04
8.19 f
u3/mul_37/FS/U27/Y (AOI21X4) 0.19
8.38 r
u3/mul_37/FS/U265/Y (OAI21X4) 0.06
8.44 f
u3/mul_37/FS/U266/Y (INVX8) 0.08
8.52 r
u3/mul_37/FS/U20/Y (NAND4X4) 0.11
8.63 f
u3/mul_37/FS/U33/Y (AOI21X4) 0.15
8.77 r
u3/mul_37/FS/U306/Y (XOR2X4) 0.18
8.95 f
u3/mul_37/FS/SUM_42_ (mul24_r_DW01_add_46_0) 0.00
8.95 f
u3/mul_37/PRODUCT_44_ (mul24_r_DW02_mult_24_24_0) 0.00
8.95 f
u3/prod_reg_44_/D (DFFXL) 0.00
8.95 f
data arrival time
8.95
clock clk (rise edge) 3.00
3.00
clock network delay (ideal) 0.00
3.00
clock uncertainty -0.10
2.90
u3/prod_reg_44_/CK (DFFXL) 0.00
2.90 r
library setup time -0.16
2.74
data required time
2.74
--------------------------------------------------------------------------
data required time
2.74
data arrival time
-8.95
--------------------------------------------------------------------------
slack (VIOLATED)
-6.21
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