Re: [fpu] Add/Sub Unit Test Vectors

[Jamil Khatib <jamilkhatib75@yahoo.com>]

Hi,

Could you please write some desicription about the
core and its interface so as to create compatible code
in  VHDL.

we should also define the specifications of the FPU
blocks interfaces

As I see the interface has:
1. signals for INF and NaN but teh core does not
encode them to the output, So do you suggest to
generate these special values in a seperate block.
2. Denormailized numbers are used as outputs so an
external block will do the normalization??
3. Do your core accept denormalized numbers? it should
do.
4. How do you handel NAN and INF numbers at the input?

Regards
Jamil KHatib

--- Rudolf Usselmann <rudi@mozart.inet.co.th> wrote:
> 
> Hi !
> 
> 
> I have written a Single Precision Pipelined Add/Sub
> Unit,
> (including all normalization blocks). I'm looking
> for test vectors
> to verify it really works correctly and covers all
> corner cases.
> My goal was to make it IEEE 754 compliant. It's not
> quite complete,
> but should be soon. I have written it in Verilog,
> and will submit
> it to open cores, if there is any interest ....
> 
> Best Regards,
> 
> rudi
> 
> rudi@inet.co.th
> 
> 
> 
> 


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