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Re: [fpu] Architecture
Well I think all your questions can be answered after we answer the main
question:
do we want a coprocessor type of FPU or a FPU that is like a functional unit
in the processor. In first case all insns with opcodes reserved for FP are
sent to the coprocessor including FP branch and alike insns. In the second
case all insns including FP are issued by the CPU core (either to the IU or
FP functional units) and the CPU core resolves structural and data hazards.
I see FPU construsted from two parts - part that actually computes (carries
out IEEE754 arithemetical operations) and part that controls operations and
optionally schedules FP insns and resolves structural and data hazards. In
case we want to make a FPU unit in a functional unit style you don't need
this second parts since CPU core resolves all hazards and does insn issue
(either in-order or OOO).
In the modern superscalar RISC processor the most common is the second
approach where FPU is one of the functional units (probably because today is
not a problem to put several million transistors on a chip that was
impossible 10-15 years ago).
regards, Damjan
----- Original Message -----
From: Jamil Khatib <jamilkhatib75@yahoo.com>
To: <fpu@opencores.org>
Sent: Tuesday, April 18, 2000 10:21 AM
Subject: [fpu] Architecture
> Hi,
> We talked about a superscaller architecture but what are the main
> execution units will be do you have any suggestion?
>
> Regarding teh instructions, should we support some program flow
> instruction, like jumps, or some stack operations? in My openion the FPU
> must consider teh program its executing as a one direction flow.
>
> How can we interface to the processor core should be a hand shack
> protocol and if the architecuter is a super scaller how can we take two
> or more instructions from teh core and what if they are dependent who
> should reorder the instructions, the FPU, the CPU core or the compiler
>
> I think we should start defining the internal FPU architecture
>
> Jamil Khatib
>
>
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