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Hi again,
I did some debugging on the original
core, which I simulated running known code and looked at what happened
inside while it was running.
The z80 databook explains states and mcycles etc -
but simply a tstate is a clock and a Mcycle (machine cycle) is a 'phase'. The
processor will first execute an instruction fetch (the first Mcycle, signal M1
is asserted) which takes 4 tstates. Then, depending on the
instruction it retrieves, a number of additional Mcycle's will
occur (each of varying tstate lengths) to execute the opcode. This is all
defined in the big case statement in the instruction decoder.
your best bet is to play with it in the simulator
...
Cheers,
Mike.
----- Original Message -----
Sent: Wednesday, January 22, 2003 2:47
PM
Subject: Re: [oc] T80 core
Actually I was hoping to find
some information on the internal lines in the system. As in the meanings of
the states in the state machine (Tstate, Mcycle) for instance. Im trying to
figure out how it works but due to the lack of comments its a difficult
battle.
jelydonut
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<-----Original
Message----->
>
> From: MikeJ
> Sent: 1/21/2003 12:59:52
PM
> To: cores@opencores.org
> Subject: Re: [oc] T80 core
>
> look for an old z80 datasheet / databook, that should tell you
everything you need to know.
> There are some examples of how to wire it
up in the distribution.
> /Mike
> ----- Original Message -----
> From: jely donut
> To: cores@opencores.org
> Sent:
Tuesday, January 21, 2003 5:13 PM
> Subject: [oc] T80 core
>
>
> I don't know if anyone will get this as this is the second
email i've sent but..
>
> Does anyone have any information on the
T80 core that is available on the site. Im looking
> perferably for any
documentation or even quick summary of the purpose of each bus/control
line.
>
> Thanks
>
> jelydonut
>
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