Re: [oc] Real newbie questions

[Niclas Hedhman <niclas@hedhman.org>]

On Sunday 19 January 2003 16:28, John Sheahan wrote:
> On Sat, Jan 18, 2003 at 12:02:46PM +0800, Niclas Hedhman wrote:
> > I recently got Protel DXP, and it gives me the impression I can design
> > FPGA/CPLD in schematic capturing, and have it output VHDL to make the
> > FPGA/CPLD.
> > Question;
> > 1. Is this actually so?
>
> a flow from schematic to vhdl to fpga would make little sense.

Well it makes sense to "Schematic people"... I look at VHDL and although being 
a programmer in every language from assembly to Java, VHDL is obscure or 
should I say "hard to get my head around".

> In a schematic - you have to instantiate paricular devies - chosen
> from a library.  What library did you use? thats the device you have
> targetted.    Perhaps there are several sized members availave.

I have several choice. For Altera and Xilinx there are libraries for different 
families, such as Spartan II(E), but there is also a more "generic" CUPL 
library, which is a smaller subset (which does fine for me).

> ypu my be able to get a structural gate vhdl netlist out - thats
> exuivilant to disassembling compiled code. May be useful for debug
> - but not very useful to port to a new architecture.
>
> Write VHDL or Verilog RTL with any decent editor (with support for the
> language) Synthesize with the free (beer) tools from Xilinx or Altera.
> I don't think schematic capture for fpga is of much relevance any more.

I will make it a shot. I will also try the synthesize tools and see how they 
react to the VHDL/CUPL netlist (and half a dozen FPGA related formats) that 
Protel outputs.

> Those tools will also allow you to fit the design into any of the
> ranges of parts they make. 192 bits of fifo is tiny - will go into
> most any fpga and some  cpld's. (unless you are doing horrible
> clocking)

"Clocking"? Well, the building blocks are Serial-to-Parallel and 
Parallel-to-Serial shifters. Separate async input and output clocks. (Input 
is dictated by the A/D converter at a continous 1Mbps stream, while the 
output is to CPU over SPI Master at 2-5Mbps, when buffer is filled.)

Anyway. Thanks for the advice. I'll get some books on the subject as well.
A search on freashmeat.net for "VHDL Editor" only reveals ChipVault for 
organization management, and "j" for syntax highlighting (The Kate editor in 
Linux KDE 3.0 has VHDL and Verilog highlighting).
I'll do more extensive searches, but are there any better tools (beyond syntax 
highlighting) available??

Niclas

> john
>
> > 2. How would I know how much can be crammed into a given FPGA?
> >
> > In particular, I need (and drew that as schematics) a asynchronous 1-bit
> > wide and 192bit deep FIFO-like circuit. Ironically, only 6pins  + power
> > is required. How do I go about selecting a device?
> >
> > Sorry for being "un-educated", but OSS is typically rather
> > "understanding", and I hope OSH is the same. Any help is greatly
> > appreciated.
> >
> > Niclas Hedhman
> > --
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