Re: [oc] Non-stalling pipeline? - I found a few things - fyi

[Ali Mashtizadeh <ali@alikat.org>]

Rudolf Usselmann wrote:
> 
> On Saturday 30 March 2002 01:10 am, you wrote:
> > http://www.sun.com/processors/UltraSPARC-III/specs.html
> >
> > Sun here says that their ultra sparc III has a 14 stage non stalling
> > pipeline. How is that possible or am i misunderstanding this?
> >
> > Ali
> 
> Well, the real question is WHY do pipelines have to be stalled
> in the first place ? I would like to suggest to view pipeline stalling
> as a design flaw in the first place. You stall a pipeline because
> you can not continue execution due to some dependency and
> or data not being available.
> 
> Sun finally sat down and "fixed" those problems. A properly
> engineered RISC should not need to stall it's pipeline.
> 
> regards,
> rudi
> 
> --
> To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml

I found some stuff but not everything. I think when they say
non-stalling pipeline they mean it only pertaining to the instruction
fetcher. Instead of freezeing everything the pipeline is allowed to
continue with nop's filling in the gaps until the instruction is
fetched. I don't know if they stall the pipeline at all due to
dependencies.

Ali
--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml