Re: [oc] Silicon Implementation

[Ali Mashtizadeh <ali@alikat.org>]

The 40K was what I got on an estimate for a gate array chip.(NEC I
believe). I do not need that much performace, I was thinking somewhere
between .25 and .8 should be enough for what I want to do(There's
several chips that I am interested in making). Remember I am moving away
from FPGA's so nobody sugest that. And I don't need these chips to last
a long time. It is more for my personal use and some friends. So if any
other company uses that Laser.. process I would like to a link to their
website. I am really looking toward gate array chips, as you said full
custom asic's are like 500K.

Ali

John Sheahan wrote:
> 
> chipexpress silicon was never what I would describe as 'real cheap'
> 
> Also there was a passivation issue that meant they were pretty much
> prototypes with very limited ife.
> 
> mask cost relates to design rules. how much performance do you need?
> 40k is at least one zero short of a current mask cost.
> john
> 
> On Sun, Mar 03, 2002 at 10:24:56PM -0800, Ali Mashtizadeh wrote:
> > I was wondering if I could get some input on how to go about
> > implementing a chip in silicon. I have considered full asic and gate
> > array. I heard chip express used to have a process with no NRE and the
> > chips were real cheap but they don't have it anymore. The name of the
> > process started with something like Laser .... I dont remember but does
> > anyone know anything like that with no NRE. I moving from FPGA's to
> > asic's. This isn't for commercial use, so if anyone knows how I can
> > implement a chip in an ASIC or gate array without paying 40K or up for
> > the NRE that would be just wonderful.
> >
> > Ali
> >
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