RE: [oc] FPGA/ASIC Design Kits

[John Clark <clarkjc@stny.rr.com>]

Liao,

Concerning the B5-Spartan2+ boards, the speed grades that Xilinx labels 
their devices with are not in ns.  Higher numbers denote faster 
devices.  Due to the complexity of their routing resources, the best way to 
estimate which speed grade is needed is to use the static timing analyzer 
software included in their development software.

- John

At 08:46 PM 12/12/2001 +0800, Liao Choon Way wrote:
>I thought the -5 rating means that the clock period is 5ns, so the 
>theoretical max clock speed is 200MHz? (usually for dev boards they give 
>you the best rated device since they don't save on volume anyway)

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