[oc] UART core; help is necessary

[Bill Simpson <yornik@iname.com>]

Hello guys,

I didn't use VHDL for two years. This week I've tried to simulate your
UART core. Unfortunately, I've failed. Would you like to help ?

1)As I understood, "uarttest.vhd" is to produce the endless cycle of
sending/receiving of 0xAA/0x55 bytes. It seems that CS_N=0 and WR_N=0
combination is wider than it's necessary and TBuff's contents is
overwriting before interrupt line set to '1'.

2) What is(was ?) the variable "tmp_TRegE" necessary for ?

3)About receiver. It seems that the sample counter is not set to zero
after bit 0 receiving.

Did anybody use OrCAD 9.1 for this UART core simulation ? At last, the
Foundation scripts/waveforms will be useful to see what is going wrong.

Thank you,
Bill Simpson