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[oc] ALDEC Vs. ModelSIM (VHDL Simulator)

To: "'cores@opencores.org'" <cores@opencores.org>
Subject: [oc] ALDEC Vs. ModelSIM (VHDL Simulator)
From: Jimmy Hui <Jimmy_Hui@avanex.com>
Date: Tue, 4 Apr 2000 10:33:11 -0700
Reply-To: cores@opencores.org
Sender: owner-cores@opencores.org

Has anyone used the ALDEC  VHDL simulator (current version is 3.6,
www.aldec.com free eval)?  How is it compared to the one by MODELSIM (Model
Technology)?

Thanks,

Jimmy

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